Computer Architecture II

Computer Science Department, St. Cloud State University, St. Cloud, MN 56301
Office ECC- 259, Phone 320-255-2142, e-mail: herath@eeyore.stcloudstate.edu

 

1. Course objectives

The objective of this course is to introduce the design concepts used in computer architectures to improve the performance of computations. Performance improvement techniques employed at instruction set, gate, register transfer, processor, memory, I/O and multiprocessor design levels will be explored to achieve the objective.

2. Course description

Computer organization and design describes how to build machines that can execute instructions at a reduced execution time or higher performance. It also describes the forces which drive the development of new organizational techniques, the decisions that must be made to develop successful computer designs, and performance criteria that can be used to make these design decisions.

The learning process of this course consists of lectures, reading assignments, problem solving sessions, hands-on laboratories, projects and tests. Lectures will enhance the knowledge given in the book chapters. It is expected that every student will read and understand the chapters. Numerous examples will be used to demonstrate problems, algorithm design and how to develop programs. Project laboratory will play a major role in this course to understand the material.

The lecture series is organized and presented in an orderly and logical transition from the computer abstractions to the concepts of multiprocessors. The material covered in this course is divided into seven sections to transfer the knowledge on computer organizations efficiently. First section introduces computer abstractions and technology, and  the role of performance. Section two focuses on the performance enhancement at instruction set design level. This will be the language of the machine used in this lecture series. Section three presents the cost reduction and speed improvement techniques for the arithmetic circuits. Section four discusses the performance enhancements at the processor design level. Data and control path design of two processors that implement the RISC instruction set will be introduced at this level. Section five  focuses on how to add a pipeline to one of the processors to enhance the performance. The role of cache and virtual memory in improving performance will be discussed next. Performance enhancements in I/O subsystems will provide the complete coverage of single processor design.  Multiprocessing to enhance the performance will be the last topic to be addressed in this lecture series. Lectures, laboratories and discussions will provide detailed presentation of examples, theory, organization, examples using organization and designs.

This course covers

the  material recommended by the IEEE Computer Society model program in computer science and engineering, and ACM curriculum recommendation for undergraduate program.

The course is intended for

future designers of digital computer systems

and it will be of great assistance to computer scientists, engineers and managers who require access to practical material and application of digital systems.

Participants will learn how to

Understand the fundamentals and strategies of digital computer designs

Use and design general purpose computer architectures

Apply techniques for analyzing, designing and improving digital computer architectures

Design state-of-the-art hardware and software

3. Textbooks required

Computer Organization and Design The Hardware/Software Interface, David A. Patterson, and John L. Hennessy,  Morgan Kaufman publishing

Experiments in Computer Architecture II by Larry Grover

Other readings

Computer Organization by Hamacher

4. Lecture outline and schedule

1. Introduction - Computer Abstractions and Technology

       Reading Assignment – chapter 1

       Homework assignment - Chapter 1 all problems

68K Laboratory Assignments

2. Performance

       Reading Assignment – chapter 2

       Homework assignment - Chapter 2 all problems

68K Laboratory Assignments

TEST –1

3. Instruction Sets

            RISC

       Reading Assignment – chapter 3

       Homework assignment - Chapter 3 problems 1, 2, 3, 4, 5, 9, 11

68K Laboratory Assignments

TEST – 2

4. Computer Arithmetic Circuits

Cost reduction and speed improvement  techniques

Flip-Flops, Boolean expressions, circuits, literal analysis, symbolic analysis,

       Reading Assignment – chapter 4

       Homework assignment - Chapter 4 all problems

X86 Laboratory Assignments

TEST – 3

5. Processor: Data Path and Control

state diagrams, mapping control to hardware, single cycle and multi-cycle implementation

       Reading Assignment – chapter 5

       Homework assignment - Chapter 5 Problems 1-25

X86 Laboratory Assignments

TEST – 4

6. Pipelining

            Enhancing performance

       Reading Assignment – chapter 6

       Homework assignment - Chapter 6  Problems 1-10

X86 Laboratory Assignments

TEST – 5

7. Large and Fast Memories

            Caches, virtual memory, improving performance

       Reading Assignment – chapter 7

       Homework assignment Chapter 7 Problems 1-10

X86 Laboratory Assignments

TEST – 6

8. Interfacing processors and peripherals

            I/O performance,  I/O devices, interfacing I/O devices to memory, processor and

operating system

       Reading Assignment – chapter 8

       Homework assignment - Chapter 8 Problems 1-10

X86 Laboratory Assignments

9. Multiprocessors

        Reading Assignment – chapter 9

        Homework assignment - Chapter 9 Problems

X86 Laboratory Assignments

 

Final Exam

CS 320 SCHEDULE Spring 2002
 

Week

What

Reading

1

Introduction

1

Lecture 1 State-of-the-art

1.1-16

2

Lecture 2 Performance

2.1–2.3

2

Performance

2.4–2.7

3

Exam

1-2

3

Lecture 3 Performance Improvement at Instruction Set level

3.1–3.3

3

Lecture 4 Translation of High Level Language Arithmetic Expressions to MIPS Code

3.4–3.5

4

Lecture 5 Translation of  Data Transfer Expressions to MIPS Code

3.6

4

Lecture 6 Translation of IfElse Switch expressions  to MIPS Code 

3.6, A.6

4

Lecture 7 Translation of Loop, for, while  expressions  to MIPS Code 

4

Lecture 8 Translation of High Level Language Procedures to MIPS Code  

3.7–3.9

Lecture 9 Architectural Styles

5

Exam

3

5

Lecture 10 Performance Enhancement by adding Functionality - ALU Design

4.1–4.3

5

Lecture 11 Performance Enhancement at Gate Level -  Adder Circuit Designs 

4.4

6

Lecture 12 Performance Enhancement at Register level - Multiplier Circuit Designs

4.6

6

Lecture 13 Performance Enhancement at Register level - Divider Circuit Designs

4.7

7

Lecture 14 Performance Enhancement at Register level - Floating point Adder Design

4.8

Lecture 15 Performance Enhancement at Register level - Floating point Multiplier

7

Exam

4

7

Lecture 16 Performance Enhancement at Processor  level - Arithmetic - Single cycle

5.1

8

Lecture 17 Performance Enhancement at Processor  level - Branch - Single

5.2

8

Lecture 18 Performance Enhancement at Processor  level  - Jump  - Single

5.2

8

Lecture 19 Performance Enhancement at Processor  level - Arithmetic, Branch, Jump 

5.3

9

Lecture 20 Controller Design

5.3

9

Lecture 21 Performance Enhancement at Processor  level - Multi Cycle implementation

5.4

10

Lecture 22 Design of Controllers  for Multi Cycle Processor  Finite State Machine

5.4- C.3

10

Lecture 23 Design of Controllers for Multi Cycle Processor - Microprogramming

5.5-C-5

11

Lecture 24 Transformation from  Finite State Machine to Micro Program

5.5

11

Exam

5

11

Lecture 25 Performance Enhancement of Processor Design - Pipelining

6.1, 6.2

12

Lecture 26 Performance Enhancement - Data hazards, stalls and forwarding

6.3

12

Lecture 27 Performance Enhancement - Branch hazards, Exceptions

6.4–6.6

12

Lecture 28 Performance Enhancement  - Superscalar and dynamic pipelining

6.8

13

Exam

6

13

Lecture 29 Performance Enhancement - Memory Hierarchy

7

13

Lecture 30 Performance Enhancement - Cache, Virtual memory

7.2–7.4

14

Lecture 31 Performance Enhancement - I/O level

8.1–8.2

14

Lecture 32 I/O

8.4–8.5

14

Lecture 33 Performance Enhancement - MultiProcessors

9.1-9.2

15

Lecture 34 MultiProcessors

9.3-9.5

15

Final Exam 

5. Laboratory Schedule

            68000 labs - Experiments in Computer Architecture II by Larry Grover

            Closed labs

Copy program  - Assign 1/16 perform  1/17, report due 1/18

                        Addressing modes - Assign  1/23, P 1/24 report due 1/25

                        More Addressing modes - Assign 1/30, perform  1/31, report due 2/1

                        Linked Data Structures - Assign 2/6 perform 2/7 report due 2/8

                        Control structures - Assign 2/13, perform  2/14, report due 2/15

                        Logic and shift instructions-Assign 2/20, perform 2/21, report due 2/22

                        Procedure protocols -Assign 2/27, perform 2/28, report due 3/1

Open Labs - Report should be submitted within two weeks after the completion of

corresponding closed lab

                        1. Name and social security number

                        2. Program relocatable code

                        3. Condition codes and Bcc

                        4. Hamming code

5. Shifting

                        6. Parity function

                        7. Recursion

                        8. Microprocessor Hardwired Control

           

X86 labs - IBM PC Programming by Marut Yu, Mc Graw Hill

Closed and open Labs

Case conversion - assign 3/6, perform 3/7, report due 3/8

            Debugging, processor status and Flags registers - a 3/20 p-3/21 R 3/22

            Flow control instructions - assign 3/27 perform 3/28 Report due 3/29

            Logic shift and Rotate instruction a- 4/3  p-4/4 Report due - 4/5   

            Stack and procedures - assign 4/10, p 4/11 Report due  4/12

            Text display and keyboard programming a 4/17, p  4/18 Report 4/19

            Game program and color graphics - a  4/24, p 4/25 Report due 4/26

I reserve the right to change the topics, or to add an item of related interest to it. However, should I do so, I will talk with you before or after class.

 

Special Note:

April 26, 2002 - Computer Science Conference at Miller Center from 8-4.30

 

6. Course requirements

            Attendance

            Completion of tests and homework

            Completion of Laboratory and project assignments

7. Grading policy (tentative)

You should perform well in all areas to receive an A in this class. In general, an A student has complete understanding, a B student is strong in many areas, a C student is weak in some concepts, and a D student is weak in many areas.

You are expected to attend all class sessions. While roll will not be taken at each class, a portion of your grade is based on your participation in classroom discussions. Missing classes will affect that portion of your grade. No make-up exams will be given during the term. If you miss assignments, and can justify the absences to my satisfaction, I will give you an assignment (probably a paper) to make up the missed one.

Examinations/quizzes are designed to test (1) your mastery of terms and concepts, and (2) your ability to apply those terms and concepts to problems posed. Short answer, multiple choice, and fill in the blank questions test the former, essay questions the latter. Two to three in-class exams will be given, along with a final.

Final grades will be based on your performance measured from the following assignments.

Projects 30%

Homework 10%

Tests 60%

           

Top 15% of the class will receive Grade A

second top 20% of the class will receive a Grade B

third top 25% of the class will receive a Grade C

next 25% of the list will receive a Grade D

rest F

If you want to dispute the grade you received for this course please  first, put your reason(s) for disputing the grade into writing. Make sure to present a legitimate grievance about your grade. Then you may send it via e-mail, or put it in my faculty mailbox. Thereafter (and *only* thereafter) make an appointment to see me to discuss it in person or by telephone.

http://www.stcloudstate.edu/stu_handbook/academic_policies/grading.html