Week

What

Reading

1

Introduction

1

Lecture 1 State-of-the-art

1.1-16

2

Lecture 2 Performance

2.1–2.3

2

Performance

2.4–2.7

3

Exam

1-2

3

Lecture 3 Performance Improvement at Instruction Set level

3.1–3.3

3

Lecture 4 Translation of High Level Language Arithmetic Expressions to MIPS Code

3.4–3.5

4

Lecture 5 Translation of  Data Transfer Expressions to MIPS Code

3.6

4

Lecture 6 Translation of IfElse Switch expressions to MIPS Code  

3.6, A.6

4

Lecture 7 Translation of Loop, for, while expressions  to MIPS Code  

4

Lecture 8 Translation of High Level Language Procedures to MIPS Code   
(Addressing Mode)

3.7–3.9

Lecture 9 Architectural Styles

5

Exam

3

5

Lecture 10 Performance Enhancement by adding Functionality - ALU Design

4.1–4.3

5

Lecture 11 Performance Enhancement at Gate Level - Adder Circuit Designs  

4.4

6

Lecture 12 Performance Enhancement at Register level - Multiplier Circuit Designs

4.6

6

Lecture 13 Performance Enhancement at Register level - Divider Circuit Designs

4.7

7

Lecture 14 Performance Enhancement at Register level - Floating point Adder Design

4.8

Lecture 15 Performance Enhancement at Register level - Floating point Multiplier

7

Exam

4

7

Lecture 16 Performance Enhancement at Processor level - Arithmetic - Single cycle

5.1

8

Lecture 17 Performance Enhancement at Processor level - Branch - Single

5.2

8

Lecture 18 Performance Enhancement at Processor level  - Jump  - Single

5.2

8

Lecture 19 Performance Enhancement at Processor level - Arithmetic, Branch, Jump  

5.3

9

Lecture 20 Controller Design

5.3

9

Lecture 21 Performance Enhancement at Processor level - Multi Cycle implementation

5.4

10

Lecture 22 Design of Controllers  for Multi Cycle Processor  Finite State Machine

5.4- C.3

10

Lecture 23 Design of Controllers for Multi Cycle Processor - Microprogramming

5.5-C-5

11

Lecture 24 Transformation from  Finite State Machine to Micro Program
Micro Programming

5.5

11

Exam

5

11

Lecture 25 Performance Enhancement of Processor Design - Pipelining

6.1, 6.2

12

Lecture 26 Performance Enhancement - Data hazards, stalls and forwarding

6.3

12

Lecture 27 Performance Enhancement - Branch hazards, Exceptions

6.4–6.6

12

Lecture 28 Performance Enhancement  - Superscalar and dynamic pipelining

6.8

13

Exam

6

13

Lecture 29 Performance Enhancement - Memory Hierarchy

7

13

Lecture 30 Performance Enhancement - Cache, Virtual memory

7.2–7.4

14

Lecture 31 Performance Enhancement - I/O level

8.1–8.2

14

Lecture 32 I/O

8.4–8.5

14

Lecture 33 Performance Enhancement - MultiProcessors

9.1-9.2

15

Lecture 34 MultiProcessors

9.3-9.5

15

Final Exam